A conventional MOS device with sub-micron dimensions is illustrated in FIG. 1. Illustratively, the device 10 is formed in a P-well region 12 of an N-type silicon substrate. N.sup.+ -type source and drain regions 14 and 16 are formed in the P-well 12. Field oxide (FOX) regions 15, 17, which are relatively thick oxide regions, separate the device 10 from adjacent devices formed on the substrate. The gate 18 is made from polysilicon. The gate 18 is separated from the P-well surface by the thin gate oxide 19 and is enclosed by the dielectric 20 which also may be oxide. The device 10 is covered by a pre-metal dielectric layer 30. The layer 30 is illustratively a dual stack of TEOS (Tetra-Ethyl-Ortho-Silicate) based USG/BPSG (Undoped Silicon Glass/Boro-Phospho-silicate Glass) with a thickness of 3000-5000 Angstroms. The layer 30 is formed by low pressure chemical vapor deposition (LPCVD) or atmospheric pressure chemical vapor deposition (APCVD).
The subject of the present invention is the formation of the metal contacts to the source and drain regions 14 and 16. These contacts are formed by etching the dielectric layer 30 to form the openings 40. The etching involves two steps, a BHF wet etch followed by anisotropic dry etch, in which steps the dielectric 30 is 40% and 60% etched, respectively. After the contact openings 40 are first formed, a reflow step is used to round the tops of the contact openings. Typically, the contact aspect ratio (depth/width)is about 1.8.
Then, the metal contacts 50 are formed in the openings 40 according to a so-called metal (I) process. A variety of processes have been suggested in the prior art for the metal (I) process and these are reviewed below. In general, the metal (I) process is used to form metal (I) contacts 50 which fill the contact openings 40. However, in order to interconnect devices formed on the surface of the same substrate, it is necessary to form vias which extend horizontally on the substrate surface (not shown in FIG. 1). To form the vias, an inter-metal dielectric involving a PECVD/SOG/PECVD (Plasma Enhanced Chemical Vapor Deposition/Spin-On-Glass/Plasma Enhanced Chemical Vapor Deposition) sandwich is formed on the substrate surface. Openings for the vias are then etched in the inter-metal dielectric. Then, the via openings are filled with metal using a metal (II) process.
In a MOSFET device with sub-micron dimensions, sub-micron metallization has been formed using the conventional W(tungsten)-CVD plug process. The W-CVD plug process has been in existence at several large device manufacturing facilities (see Y. Takata et al VMIC 1991, p. 13). The W-CVD plug process has been successfully used for multilevel interconnection.
However, the W-CVD plug process has a number of significant disadvantages. It is a high cost process and requires additional process steps. It also requires a more planarized surface topography owing to the subsequent process of residue free tungsten etchback.
Instead of using the tungsten plug process to form metallization, an Al-based metallization process may be used. The advantages of an aluminum based metallization process are that a well understood material is used, there is a simpler process sequence, and a perceived lower cost.
The conventional aluminum process for forming the metal (I) contact may be understood in connection with FIG. 2. A conventional sputtering machine is used.
The steps for forming the metal (I) contact 50 in the opening 40 are as follows:
(1) Buffer Oxide Etch (BOE) to remove native oxide from contact openings of the wafer; PA1 (2) in the sputtering machine, grow a layer of Ti with a thickness of about 400 .ANG. in the contact openings; PA1 (3) in the sputtering machine, grow a layer of TiN with a thickness of about 1000 .ANG. in the contact opening; (The sputtering steps (2) and (3) take place in a vacuum maintained in a chamber of the sputtering machine. The vacuum is 10.sup.-5 to 10.sup.-8 Torr. The Ti layer is labeled 52 in FIG. 2 and the TiN layer is labeled 54.) PA1 (4) The wafer is removed from the sputtering chamber and exposed to air; PA1 (5) The wafer is annealed at a temperature of about 450 degrees for about 30 minutes; PA1 (6) The wafer is then returned to the sputtering machine and an aluminum based layer with a thickness of 4500-10,000 Angstroms is deposited by sputtering at a temperature of about 300.degree. C. (The aluminum based layer is labeled 56 in FIG. 2.) The aluminum based layer 56 may be an Al-Si-Cu alloy or other Al-based alloy. As shown in FIG. 1, the aluminum based layer 56 is then etched to form the metal contacts 50 over the source and drain regions 14, 16. PA1 (7) The wafer is then moved to another chamber and a TiN layer (not shown in FIG. 2) is deposited by sputtering with a thickness of about 400 Angstroms to serve as a anti-reflection coating (ARC).
Then the inter-metal dielectric (IMD) layers are formed. The wafer than goes to X-ray lithography to pattern the IMD to form via openings for the vias formed by a metal (II) process.
The purpose of the Ti/TiN layers is to prevent aluminum from diffusing into the silicon substrate. The Ti/TiN layers thus serve as a barrier for aluminum diffusion. If the Ti/TiN barrier is not good enough and aluminum diffuses through the barrier into the silicon substrate, there will be junction leakage and device failure. The purpose of the vacuum break and anneal steps is to fill the grain boundaries of the Ti/TiN layers so that the aluminum and silicon do not diffuse together in the subsequent aluminum deposition step.
An important problem with the conventional Al/Si/Cu metallization process is poor Al step coverage. A higher Al/Si/Cu deposition temperature, such as 450.degree. C., is used to overcome the poor Al step coverage. However, a significant problem with the conventional high temperature Al/Si/Cu metallization process is the precipitation of silicon nodules that resist etching as the Al/Si/Cu layer is cooled to room temperature. This is due to the high solubility of Si in Al at high temperatures, but low solubility of Si in Al at low temperatures. Referring to FIGS. 1 and 2, the etch resistant silicon nodules, which precipitate in the aluminum based layer 56 and on its surface, prevent etching and removal of the aluminum based layer 56 from the surface of the dielectric layer 30 located between the two metal contacts 50. Therefore, the precipitated silicon nodules cause device failure due to metal bridging or shorting between the two contacts 50 of the source and drain regions 14, 16.
Accordingly, it is an object of the invention to provide an Al-based contact formation process which overcomes the shortcomings of the prior art.
In particular, it is an object of the invention, to provide an Al-based contact formation process which is useful in sub-micron device geometries, and which prevents the formation of silicon nodule precipitates that resist etching.